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Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
FEATURES
* Three banks of outputs: one bank of two LVDS outputs and two banks of one LVPECL output * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended reference clock input * Four independently selectable output frequency on each bank: 318.75MHz, 212.5MHz, 159.375MHz and 106.25MHz * Maximum output frequency: 318.75MHz * Crystal input frequency: 25.5MHz * VDDO_LVPECL can be set for 3.3V or 2.5V, allowing the device to generate 3.3V or 2.5V LVPECL levels * RMS phase jitter at 106.25MHz, using a 25.5MHz crystal (637kHz to 10MHz intergration): 2.65ps (typical)
GENERAL DESCRIPTION
The ICS843404 is a low phase noise Fibre Channel Clock Generator and is a member of HiPerClockSTM the HiPerClockSTM family of high performance clock solutions from ICS. The device provides two banks of one LVPECL output per bank and one bank of two LVDS outputs. Each bank can be independently set by using their respective frequency select pins for the following output frequencies: 318.75MHz, 212.5MHz, 159.375MHz or 106.25MHz, using a 25.5MHz 18pF parallel resonant crystal. The ICS843404 can also be driven from a 25.5MHz single-ended reference clock. For system debug or test purposes, the PLL can be bypassed using the VCO_SEL pin.
IC S
PIN ASSIGNMENT
MR VCO_SEL VDDo_LVDS LVDS0 nLVDS0 LVDS1 nLVDS1 nc LVPECL_FSELB0 LVPECL_FSELB1 nc VDDA LVPECL_FSELA0 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LVDS_FSEL0 LVDS_FSEL1 VDDO_LVPECL LVPECLA0 nLVPECLA0 LVPECLB0 nLVPECLB0 XTAL_SEL TEST_CLK GND GND XTAL_IN XTAL_OUT LVPECL_FSELA1
Offset Noise Power 100Hz ................. -89.1 dBc/Hz 1kHz ................. -112.7 dBc/Hz 10kHz ................. -128.0 dBc/Hz 100kHz ................. -130.2 dBc/Hz * Supply voltage modes: * VDD = VDDA = 3.3V * VDDO_LVPECL = 3.3V or 2.5V * VDDO_LVDS = 3.3V * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages * Industrial termperature information available upon request
ICS843404
28-Lead TSSOP, 173-MIL 4.4mm x 9.7mm x 0.92mm body package G Package Top View
BLOCK DIAGRAM
VCO_SEL Pullup
LVPECL_FSELA1:0
VDDO_LVPECL
00 01 10 11 0 0 00 01 10 11
/2 /3 /4 /6 /2 /3 /4 /6
LVPECLA0 nLVPECLA0
TEST_CLK Pulldown
25.5MHz
LVPECL_FSELB1:0
LVPECLB0 nLVPECLB0
XTAL_IN XTAL_OUT XTAL_SEL Pullup
OSC
1
Phase Detector
VCO 637.5MHz
(Fixed)
1
LVDS_FSEL1:0
LVDS0 nLVDS0
M = 25 (fixed)
00 01 10 11
/2 /3 /4 /6
LVDS1 nLVDS1 MR Pulldown
843404AG
VDDO_LVDS
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1
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Type Description Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs LVPECLx/LVDSx to go low and the Pulldown inver ted outputs nLVPECLx/nLVDSx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. VCO select pin. When HIGH, PLL is enabled. When LOW, PLL is in Pullup Bypass mode. LVCMOS/LVTTL interface levels. Output supply pin for LVDS outputs. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. No connect. Frequency select pin for LVPECLB outputs. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Frequency select pin for LVPECLB outputs. See Table 3B. Pullup LVCMOS/LVTTL interface levels. Analog supply pin. Frequency select pin for LVPECLA outputs. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Frequency select pin for LVPECLA outputs. See Table 3B. Pullup LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Pullup Reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number Name
1
MR
Input
2 3 4, 5 6, 7 8, 11 9 10 12 13 14 15 16, 17 18, 19 20 21 22, 23
VCO_SEL VDDO_LVDS LVDS0, nLVDS0 LVDS1, nLVDS1 nc LVPECL_FSELB0 LVPECL_FSELB1 VDDA LVPECL_FSELA0 VDD LVPECL_FSELA1 XTAL_OUT, XTAL_IN GND TEST_CLK XTAL_SEL
Input Power Output Output Unused Input Input Power Input Power Input Input Power Input Input
nLVPECLB0, Output Differential output pair. LVPECL interface levels. LVPECLB0 nLVPECLA0, 24, 25 Ouput Differential output pair. LVPECL interface levels. LVPECLA0 26 VDDO_LVPECL Power Output supply pin for LVPECL outputs. LVDS_FSEL1, Frequency select pins for LVDS outputs. See Table 3A. 27, 28 Input Pulldown LVDS_FSEL0 LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
843404AG
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REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
LVDS Output Frequency (MHz) (25.5MHz Crystal) 318.75 (default) 212.5 159.375 106.25
TABLE 3A. LVDS FREQUENCY SELECT FUNCTION TABLE
Inputs LVDS_FSEL1 0 0 1 1 LVDS_FSEL0 0 1 0 1 LVDS Output Divider 2 3 4 6
TABLE 3B. LVPECLA0 FREQUENCY SELECT FUNCTION TABLE
Inputs LVPECL_FSELA1 0 0 1 1 LVPECL_FSELA0 0 1 0 1 LVPECLA0 Output Divider 2 3 4 6 LVPECLA0 Output Frequency (MHz) (25.5MHz Crystal) 318.75 212.5 159.375 (default) 106.25
TABLE 3C. LVPECLB0 FREQUENCY SELECT FUNCTION TABLE
Inputs LVPECL_FSELB1 0 0 1 1 LVPECL_FSELB0 0 1 0 1 LVPECLB0 Output Divider 2 3 4 6 LVPECLB0 Output Frequency (MHz) (25.5MHz Crystal) 318.75 212.5 159.375 (default) 106.25
843404AG
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REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V 50mA 100mA 10mA 15mA 49.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVPECL Outputs) Continuous Current Surge Current Outputs, IO (LVDS Outputs) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_LVPECL = VDDO_LVDS = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO_LVPECL VDDO_LVDS IDD IDDA IDDO_LVPECL IDDO_LVDS Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 3.135 Typical 3.3 3.3 3.3 3.3 100 25 20 55 Maximum 3.465 3.465 3.465 3.465 Units V V V V mA mA mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO_LVPECL = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO_LVPECL IDD IDDA IDDO_LVPECL Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 70 20 20 Maximum 3.465 3.465 2.625 Units V V V mA mA mA
843404AG
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4
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO_LVPECL = VDDO_LVDS = 3.3V5%,
VDD = VDDA = 3.3V5%, VDDO_LVPECL = 2.5V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage TEST_CLK, MR, LVPECL_FSELA0, LVPECL_FSELB0, Input LVDS_FSEL0, LVDS_FSEL1 High Current LVPECL_FSELA1, LVPECL_FSELB1, VCO_SEL, XTAL_SEL TEST_CLK, MR, LVPECL_FSELA0, LVPECL_FSELB0, Input LVDS_FSEL0, LVDS_FSEL1 Low Current LVPECL_FSELA1, LVPECL_FSELB1, VCO_SEL, XTAL_SEL Test Conditions Minimum Typical 2 -0.3 VDD = VIN = 3.465V Maximum VDD + 0.3 0.8 150 Units V V A
IIH
VDD = VIN = 3.465V
5
A
VDD = 3.465V, VIN = 0V
-5
A
IIL
VDD = 3.465V, VIN = 0V
-150
A
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO_LVPECL = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VDDO_LVPECL - 1.4 VDDO_LVPECL - 2.0 0.6 Typical Maximum VDDO_LVPECL - 0.9 VDDO_LVPECL - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VDDO_LVPECL - 2V.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO_LVDS = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 4 1.35 5 Maximum Units mV mV V mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical Maximum 25.5 50 7 1 Units MHz pF mW Fundamental
843404AG
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5
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Test Conditions Minimum Typical 25.5 318.75 LVDS LVPECL 318.75MHz (12kHz - 20MHz) LVPECL 212.5MHz (1.274MHz - 20MHz) 159.375MHz (12kHz- 20MHz) 106.25MHz (637kHz - 10MHz) 318.75MHz (12kHz - 20MHz) LVDS 212.5MHz (1.274MHz - 20MHz) 159.375MHz (12kHz- 20MHz) 106.25MHz (637kHz - 10MHz) 3.22 3.18 3.06 2.65 2.84 2.93 4.32 3.81 1 20% to 80% 350 850 30 65 585 Maximum Units MHz MHz ps ps ps ps ps ps ps ps ps ps ps ms ps %
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO_LVPECL = VDDO_LVDS = 3.3V5%, TA = 0C TO 70C
Symbol fIN fMAX t sk(b) t sk(o) Parameter Cr ystal Input Frequency Output Frequency Bank Skew; NOTE 1
Output Skew; NOTE 2, 3
t jit(O)
RMS Phase Jitter, (Random); NOTE 4
tL tR / tF
PLL Lock Time Output Rise/Fall Time
odc Output Duty Cycle 48 52 NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross point. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: All phase noise plots are taken using 25.5MHz cr ystal. Refer to the Phase Noise Plots on the next page.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO_LVPECL = 2.5V5%, TA = 0C TO 70C
Symbol fIN fMAX t sk(b) t sk(o) Parameter Cr ystal Input Frequency Output Frequency Bank Skew; NOTE 1 LVDS LVPECL 318.75MHz (12kHz - 20MHz) LVPECL t jit(O) RMS Phase Jitter, (Random); NOTE 4 LVDS 212.5MHz (1.274MHz - 20MHz) 159.375MHz (12kHz- 20MHz) 106.25MHz (637kHz - 10MHz) 318.75MHz (12kHz - 20MHz) 212.5MHz (1.274MHz - 20MHz) 159.375MHz (12kHz- 20MHz) 106.25MHz (637kHz - 10MHz) tL tR / tF PLL Lock Time Output Rise/Fall Time 20% to 80% 350 2.84 4.22 4.74 3.96 2.84 2.93 4.32 3.81 1 850 Test Conditions Minimum Typical 25.5 318.75 30 65 585 Maximum Units MHz MHz ps ps ps ps ps ps ps ps ps ps ps ms ps %
Output Skew; NOTE 2, 3
odc Output Duty Cycle 48 52 NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross point. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: All phase noise plots are taken using 25.5MHz cr ystal. Refer to the Phase Noise Plots on the next page.
843404AG
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6
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Fibre Channel Filter 106.25MHz
RMS Phase Jitter (Random) 637kHz to 10MHz = 2.65ps (typical)
0 -10 -20 -30 -40
TYPICAL PHASE NOISE AT 106.25MHZ FOR LVPECL
NOISE POWER dBc Hz
-50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150
Raw Phase Noise Data
-170 -180 -190 10 100 1k
Phase Noise Result by adding Fibre Channel Filter to raw data
10k 100k 1M 10M 100M
-160
0 -10 -20 -30 -40
TYPICAL PHASE NOISE AT 106.25MHZ FOR LVDS
Fibre Channel Filter 106.25MHz
RMS Phase Jitter (Random) 637kHz to 10MHz = 3.81ps (typical)
NOISE POWER dBc Hz
-50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150
-170 -180 -190 10 100 1k 10k
OFFSET FREQUENCY (HZ)
843404AG
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7
-160
OFFSET FREQUENCY (HZ) Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data
100k
1M
10M
100M
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VDD, VDDA, VDDO_LVPECL
Qx
SCOPE
Qx
3.3V5% POWER SUPPLY + Float GND -
SCOPE
LVPECL
nQx
LVDS
nQx
GND
-1.3V0.165V
LVPECL 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.8V0.04V 2V
LVDS 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
VDD, VDDA, VDDO_LVPECL
Qx
SCOPE
LVPECL
GND
nQx
Phase Noise Mask
-0.5V0.125V
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVPECL 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nLVPECLx, nLVDSx LVPECLx, LVDSx nLVPECLy, nLVDSy LVPECLy, LVDSy
nLVPECLx, nLVDSx LVPECLx, LVDSx
Pulse Width t PERIOD
tsk(o)
OUTPUT SKEW
843404AG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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8
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
nLVDS0
80%
LVDS0 nLVDS1 LVDS1
80% VOD
Clock Outputs
20% tR tF
20%
tsk(b)
LVDS BANK SKEW (MAXIMUM VALUE)
LVDS OUTPUT RISE/FALL TIME
VDDO_LVDS out
80% Clock Outputs
80% VSW I N G
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
LVPECL OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDDO_LVDS
out
DC Input
LVDS
100
VOD/ VOD out
REV. A OCTOBER 17, 2005
DIFFERENTIAL OUTPUT VOLTAGE SETUP
843404AG
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9
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843404 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO_X should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA. The 24 resistor can also be replaced by a ferrite bead.
3.3V VDD .01F VDDA .01F 10F 24
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843404 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25.5MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 18p X1 18pF Parallel Crystal XTAL_IN C2 22p
ICS843404
Figure 2. CRYSTAL INPUt INTERFACE
843404AG
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10
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT: For applications not requiring the use of the clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS OUTPUT All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V 3.3V LVDS_Driv er + R1 100
-
100 100 Differential Transmission Line Ohm Differiential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
843404AG
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REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
843404AG
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12
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VDD - 2V. For VDDO = 2.5V, the VDDO - 2V is very close to
2.5V
2.5V 2.5V VDDO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VDDO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VDDO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
843404AG
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13
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
LAYOUT GUIDELINE
Figure 6 shows a schematic example of the ICS843404. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel resonant 25.5MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
VDDO
U1 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R7 24 C5 0.1u MR LVDS_FSEL0 VCO_SEL LVDS_FSEL1 VDDO_LVDS VDDO_LVPECL LVDS0 LVPECLA0 nLVDS0 nLVPECLA0 LVDS1 LVPECLB0 nLVDS1 nLVPECLB0 nc XTAL_SEL LVPECL_FSELB0 TEST_CLK LVPECL_FSELB1 GND nc GND VDDA XTAL_IN LVPECL_FSELA0 XTAL_OUT VDD LVPECL_FSELA1 ICS843404 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Zo = 50 + Zo = 50 R2 50 R1 50
X1
25.5 MHz C2 22pF C1 18pF
R3 50
C3 10u
C4 0.1u Zo = 50 + R4 100 Zo = 50 -
(U1,3)
C6 0.1u
VDDO
(U1,26)
C7 0.1u
VDD = 3.3V VDDO = 3.3V
FIGURE 6. ICS843404 SCHEMATIC EXAMPLE
843404AG
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REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843404. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843404 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IDD_TYP = 3.465V * 100mA = 346.5mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 60mW = 406.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.407W * 43.9C/W = 87.8C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 28-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 82.9C/W 49.8C/W
200
68.7C/W 43.9C/W
500
60.5C/W 41.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843404AG
www.icst.com/products/hiperclocks.html
15
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
DD
*
For logic high, VOUT = V (V
DDO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
DDO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
DD_MAX
- 2V))/R ] * (V
L
DD_MAX
-V
OH_MAX
) = [(2V - (V
DD_MAX
-V
OH_MAX
))/R ] * (V
L
DD_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
DD_MAX
- 2V))/R ] * (V
L
DD_MAX
-V
OL_MAX
) = [(2V - (V
DD_MAX
-V
OL_MAX
))/R ] * (V
L
DD_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843404AG
www.icst.com/products/hiperclocks.html
16
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 82.9C/W 49.8C/W
200
68.7C/W 43.9C/W
500
60.5C/W 41.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843404 is: 2314
843404AG
www.icst.com/products/hiperclocks.html
17
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
28 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 9.60 6.40 BASIC 4.50 Millimeters Minimum 28 1.20 0.15 1.05 0.30 0.20 9.80 Maximum
Reference Document: JEDEC Publication 95, MO-153
843404AG
www.icst.com/products/hiperclocks.html
18
REV. A OCTOBER 17, 2005
Integrated Circuit Systems, Inc.
ICS843404
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR
Package 28 Lead TSSOP 28 Lead TSSOP 28 Lead "Lead Free" TSSOP 28 Lead "Lead Free" TSSOP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843404AG ICS843404AGT ICS843404AGLF ICS843404AGLFT Marking ICS843404AG ICS843404AG ICS843404AGLF ICS843404AGLF
NOTE: Pats that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843404AG
www.icst.com/products/hiperclocks.html
19
REV. A OCTOBER 17, 2005

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